Research Article
Modified PFAL Adiabatic Technique for Low Power
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Communications on Applied Electronics
Foundation of Computer Science (FCS), NY, USA
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| Volume 3 - Issue 7 |
| Published: December 2015 |
| Authors: Bhakti Patel, Poonam Kadam |
10.5120/cae2015652000
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Bhakti Patel, Poonam Kadam . Modified PFAL Adiabatic Technique for Low Power. Communications on Applied Electronics. 3, 7 (December 2015), 40-43. DOI=10.5120/cae2015652000
@article{ 10.5120/cae2015652000,
author = { Bhakti Patel,Poonam Kadam },
title = { Modified PFAL Adiabatic Technique for Low Power },
journal = { Communications on Applied Electronics },
year = { 2015 },
volume = { 3 },
number = { 7 },
pages = { 40-43 },
doi = { 10.5120/cae2015652000 },
publisher = { Foundation of Computer Science (FCS), NY, USA }
}
%0 Journal Article
%D 2015
%A Bhakti Patel
%A Poonam Kadam
%T Modified PFAL Adiabatic Technique for Low Power%T
%J Communications on Applied Electronics
%V 3
%N 7
%P 40-43
%R 10.5120/cae2015652000
%I Foundation of Computer Science (FCS), NY, USA
Abstract
This paper presents the quasi-adiabatic Modified Positive Feedback Adiabatic Logic (MPFAL) for low power operation through energy recovery technique. The circuit of positive feedback adiabatic (PFAL) inverter has been improved here. It is a diode-free and dual rail logic offering both the true and complementary outputs. Validation is done through basic digital gate circuits. Comparison with static CMOS and PFAL circuits are made to prove the designs. In post-layout simulations, energy savings of 27% is achieved against the optimized PFAL Inverter, NAND and NOR gate circuits. The various improvement results are analyzed in LTSPICE tool.
References
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